كبير مهندسي التصميم الفيزيائي (Floorplan & PnR)

THE ROLE A good floorplan makes every stage that follows easier, and a bad one haunts the project to tapeout. You'll own the implementation side of physical design, from partitioning and power planning through placement, CTS and routing, on some of the most advanced technology nodes out there. WHAT YOU'LL DO Own floorplanning, partitioning, pin assignment and power mesh design at block and full chip level Run placement, CTS, routing and optimisation to close PPA targets Drive clock tree planning and analysis, and scan reordering Close physical verification: DRC, LVS, antenna, ERC Resolve EM/IR issues and contribute to low power implementation Work closely with STA, DFT and RTL teams through to signoff Complete multiple design cycles with little supervision

Desired Candidate Profile

WHAT WE'RE LOOKING FOR 10+ years of RTL to GDSII experience on 10nm or below nodes, with designs of 500k to 1M+ instances Power user of PnR tools from Synopsys and/or Cadence (ICC2, Fusion Compiler, Innovus) Excellent floorplan, power plan, CTS, place, route and timing closure skills Strong EM/IR, DRC, LVS and ERC analysis and fixing Good knowledge of synthesis and DFT scan insertion Proficiency in Tcl, Perl, Python and Makefile Tapeout experience; top level floorplanning is a plus YOU'LL THRIVE HERE IF YOU You can look at a floorplan and see the congestion before the tool does You enjoy the puzzle of balancing power, performance and area You work well on your own and still keep the wider team in the loop You take pride in a clean DRC and LVS run You want to work at the leading edge of process technology